1. Field of the Invention
The present invention relates to a method of forming a gate structure, and more particularly, to a method of forming a notched gate structure.
2. Description of the Prior Art
The accelerating rate of improvement in the performance of advanced generations of CMOS IC's has been enabled by the aggressive scaling of the minimum lithographic feature size and supply voltages as well as innovations in transistor structure, and the addition of higher-levels of systems functionality of the IC design.
Fabrication of a metal oxide semiconductor field-effect transistor (“MOSFET”) device is well known. As the dimension of the device shrinks to several nm, the parasitic capacitance between the gate and the source/drain extension increases in importance but limits the performance and the electrical quality of the MOSFET. Therefore, a notched gate structure is provided in order to reduce the parasitic capacitance between the gate and the source/drain extension. However, the notched gate structure of the conventional process uses isotropic etching. When performing the isotropic etching, the notched structure and the size are not easily controlled due to some processes having the same etching ratio. Therefore, the yield of the semiconductor devices and the throughout of product are limited.
As semiconductor devices become increasingly integrated, the line width becomes smaller. The etching result is difficult of control by using the notched gate structure to reduce the parasitic capacitance between the gate and the source/drain extension. The stability of devices are further influenced, thereby resulting in greater difficulty in fabricating the smaller semiconductor devices and reduces the yield and the electrical quality of devices.
Therefore, the present invention provides a method of forming a notched gate structure in order to overcome the disadvantages existing in the conventional process.